I spent 3 years in the industry after my undergraduate degree, prior to joining CMU. While at CMU, I spent two summers in the industry. Working in systems research, this exposure to industry has been valuable and has helped me understand some of the challenges and design considerations to get a system running in the real-world.
Internships during PhD
Apple Inc., Cupertino, Summer 2015
Role: Intern in Wireless Technologies group under guidance of Dr. Brent Ledvina
Project: Experimental work on a ranging technology
I worked on the earliest experiments, prototype and preliminary modeling of time-of-flight RF ranging technology in the location team, and was selected to present the work and demonstrate a prototype to Craig Federighi, SVP of Software Engineering, Apple. Subsequently, this resulted in product impact.
Texas Instruments R&D, Dallas, Summer 2013
Role: R&D Intern in Embedded Processing Team, under guidance of Dr. Srinath Hosur and Dr. Ariton Xhafa
Project: Hybrid communication over power line and WiFi
I analyzed the feasibility of integrating wireless and power line communication technologies and designed and simulated co-existence of both technologies at the MAC and PHY layer.
Signals & Systems India Pvt. Ltd., Chennai, India, Aug’09-Jul’11
Role: Research and Development Engineer
Project: Design of embedded products for power sector
I designed energy metering products, primarily working on the embedded software. I worked on early versions (LPC2378, ADE7758-based) of the Reference Energy Meters and the Multi Function Transducers that you can see here
. I was part of the product development process from customer specifications to deployment and worked closely with the hardware and production teams. I had a chance to implement the DLMS communication stack for metering applications, which was quite new for the metering products during that time.
Analog Devices Inc., Bangalore, India, Jun‘08–Jul‘09
Role: IC Design Engineer in the SHARC DSP Group
Project: SHARC 2146x-2148x verification
I designed and implemented the Test Plan for the Variable Instruction Set Architecture and verified the Core and IOP modules at the RTL and Gate Level.